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PCI Express 4.0 Lane Margining | DesignWare IP | Synopsys
BXELK-TN-002: Non-intrusive continuous multi-gigabit transceivers link
Test and Debug of PCIe, SAS, and SATA | Tektronix
Measured eye diagrams of the PCIe channel with the compliance card
PCIe, diagnosing and improving eye diagram - NXP Community
ADS Workshop on PCI Express(r)
"Eye" Diagram of a Digital Signal
Building high-performance interconnects with multiple PCIe generations
PCIe PHY Design and Integration Success — Rambus Technical Article